Hardware accelerator for finite element iterative methods
D. Moloney · 2005
An accelerator for linear algebra kernel functions is described, in particular the sparse-matrix by vector multiplication (SMVM) computation which is at the heart of all finite element calculations. The proposed architecture seeks to accelerate the key performance-limiting SMVM operation at the heart of these applications through a combination of a dedicated datapath optimized for these applications, in particular by incorporating direct support for symmetric matrices, and SMVM (sparse-matrix by vector multiplication) to dot-product (DDOT) chaining. System simulations performed using a cycle-accurate C++ architectural model and a database of over 100 large symmetric matrices demonstrate that a 20% average FLOPs/cycle performance improvement can be achieved for the symmetric case.