Custom Built Heterogeneous Multi-core Architectures (CUBEMACH): Breaking the conventions
Venkateswaran Nagarajan, Karthikeyan Palavedu Saravanan, Nachiappan Chidambaram Nachiappan, Aravind Vasudevan, Balaji Subramaniam, Ravindhiran Mukundarajan · 2010
Increasing computational demand has stirred node architectures to move towards SuperComputer-On-Chips(SCOCs), where computational efficiency is emphasized over peak performance. Suitability of the architecture to a wider class of applications is becoming an pre-eminent design constraint for future HPC systems. This paper explores a novel design paradigm, the Custom Built Heterogeneous Multi-core Architectures (CUBEMACH) for realizing future generation node architectures. The CUBEMACH design flavoring a set of applications offers the possibility of increased resource utilization, which is exploited by running traces of multiple independent applications within a node without time or space sharing. A wide variety of complex Algorithm Level Functional units (ALFUs) besides scalars are used to meet high performance requirements of the grand challenge applications. To cater to the high communication bandwidth requirements across heterogeneous cores comprising these Algorithm Level Functional Units, a novel hierarchical communication backbone structure referred to as the On-Node-Network (ONNET) is used. The demand for high instruction issue rate due to the presence of a large number Algorithm Level Functional Units is catered by an Hardware based Compiler-On-Silicon(COS). The cost-effectiveness is achieved due to the the fact that the CUBEMACH design paradigm helps create an architecture for a single user for executing multiple independent applications without space time sharing.The cost effectiveness of implementing the CUBEMACH Design Paradigm is also achieved by developing SCOC IP cores for Higher Level Functional Us, Compiler-On-Silicon and On-Node-Network.