Validation in a component-based design flow for multicore SoCs
Gabriela Nicolescu, Sungjoo Yoo, Aimen Bouchhima, Ahmed Amine Jerraya · 2002
Currently, since many SoCs include heterogeneous components such as CPUs, DSPs, ASICs, memories, buses, etc., system integration becomes a major step in system design. To enable this integration, we use a design approach called component based-design approach. In this design approach, the validation of system implementation is a bottleneck in the design cycle. Most of design efforts are devoted to it. This paper presents a validation method for SoCs design. Based on a generic simulation wrapper architecture, the presented method provides automatic generation of executable models throughout different stages of SoC design flow. A case study of validating a VDSL application shows the effectiveness of the method.