Multilevel error correction scheme for MLC flash memory
Zhiqiang Cui, Zhongfeng Wang, Xinming Huang · 2014
Storing multiple bits in a flash memory cell is a primary technique to linearly increase flash memory capacity, but memory endurance is tremendously sacrificed. This paper presents a multilevel fault tolerance technique for MLC flash memories. The main idea is to explore multi-level forward error correction (FEC) for multiple bits in a flash cell. The associated practical implementation issues are well addressed in this paper. Compared to the conventional error protection methods for flash memory, the proposed multi-level FEC approach can obtain much larger system coding gain using the same amount of redundant bits. As a result, the proposed technique reduces power consumption considerably compared to the conventional methods since the required throughout of LDPC codec is drastically reduced. It can also increase flash memory endurance as it can allocate more redundancy to LDPC code while maintaining overall redundancy ratio.