Finding best voltage and frequency to shorten power-constrained test time
Praveen Venkataramani, Suraj Sindia, Vishwani D. Agrawal · 2013
In a digital test, supply voltage (VDD), clock frequency (ftest), peak power (PMAX) and test time (TT) are related parameters. For a given limit PMAX= PMAX func, normally set by functional specification, we find the optimum VDD= VDDoptand ftest= foptto minimize TT. A solution is derived analytically from the technology-dependent characterization of semiconductor devices. It is shown that at VDDoptthe peak power any test cycle consumes just equals PMAX funcand ftestis fastest that the critical path at VDDoptwill allow. The paper demonstrates how test parameters can be obtained numerically from MATLAB, or experimentally by bench test equipment like National Instruments' ELVIS. This optimization can cut the test time of ISCAS'89 benchmarks in 180nm CMOS into half.