FPGA Implementation of Image Compression Algorithm Using Bottom-up Approach of Quad Tree Technique
SatishK Shah, RakeshK Soni, Brijesh N. Shah · IETE Journal of Research · 2011
AbstractThis paper presents an optimal technique for image compression by which one can achieve maximal storage and transmission capabilities. Realizing image compression hardware into a Field Programmable Gate Array (FPGA) reduces the implementation cost as well as the prototyping and design time cycle. Aggressive algorithm to architecture mapping of a Quad Tree based image compression method produces a fast, compact pipelined design. Mapped into a Xilinx Spartan II, XC200S-5PQ208 FPGA, this design utilizes as much as half the resources that other algorithms such as Discrete Cosine Transform and Wavelet Transform use. Performance of this implementation exceeds those of similar and or greater resource size, and allows for real-time image compression of an image up to 256 pixels by 256 pixels at 256 levels of gray. It is found that the algorithm provides a high compression ratio ranging between 0.12 and 0.68.