Statistical modeling and post manufacturing configuration for scaled analog CMOS
Gokce Keskin, Jonathan E. Proesel, Larry Pileggi · 2010
Process variations in advanced CMOS process nodes limit the benefits of scaling for analog designs. In the presence of increasing random intra-die variations, mismatch becomes a significant design challenge in circuits such as comparators. In this paper we describe and demonstrate the details of a statistical element selection (SES) methodology that relies on choosing a subset of selectable circuit elements (e.g., input transistors in a comparator) to achieve the desired specification (e.g., offset). Silicon results from a 65nm test chip demonstrate that SES can achieve an order of magnitude better matching than both redundancy and Pelgrom-model sizing given the same core circuit area.