A flexible hardware architecture for 2-D discrete wavelet transform
Richard M. Carbone, Andreas E. Savakis · 2004
We present the design and implementation of a flexible hardware architecture used to perform the 2-D Discrete Wavelet Transform (DWT). A generic VHDL IP core is developed that is configurable to perform the forward and inverse 2-D DWT on an image using a user-defined biorthogonal wavelet. The DWT is performed using the hardware-efficient Lifting Scheme method versus the traditional convolution-based methods minimizing memory requirements, eliminating the need for expensive floating-point arithmetic, and increasing speed. This DWT core is synthesized to a Xilinx Virtex FPGA and configured to perform the Cohen-Dabuechies-Feaveau 5/3 and 9/7 DWTs, which are used in the JPEG2000 still image compression standard.