Design and implementation of floating point multiplier based on Vedic Multiplication Technique
Aniruddha Kanhe, Shishir Kumar Das, Ankit Kumar Singh · 2012
In this paper, Vedic Multiplication Technique is used to implement IEEE 754 Floating point multiplier. The Urdhva-triyakbhyam sutra is used for the multiplication of Mantissa. The underflow and over flow cases are handled. The inputs to the multiplier are provided in IEEE 754, 32 bit format. The multiplier is implemented in VHDL and Virtex-5 FPGA is used.