A Tiny Scale VLIW Processor for Real-Time Constrained Embedded Control Tasks
Oliver Stecklina, M. Methfessel · 2014
In this paper we present the architectural design of the tiny scale very long instruction word (VLIW) soft-core processor TinyVLIW8. The processor is designed to achieve a minimal instruction execution time and design size. Although, the instruction repertoire is not large, it is dequate for control tasks, which require decision making that could not easily be implemented in an application specific integrated circuit (ASIC) and in which an extensive mathematical processing is not required. Especially in the area of embedded control tasks with real-time requirements an architecture using single-cycle instructions is key. We will illustrate an application of our TinyVLIW8 by presenting an design of a secure wake-up receiver for low power wireless sensor nodes. To the best of our knowledge, the presented soft-core processor is the smallest VLIW design with an average instruction execution time of one clock cycle only. The core consumes less than 6% of the logic cells of the smallest Altera Cyclone IV FPGA and can be used in a system-on-chip design as well.