A New Metal Control Gate Last process (MCGL process) for high performance DC-SF (Dual Control gate with Surrounding Floating gate) 3D NAND flash memory
Yoohyun Noh, Youngsoo Ahn, Hyun-Seung Yoo, Byeongil Han, Sung‐Jae Chung, Keonsoo Shim, Keunwoo Lee, Sanghyon Kwak, Sung‐Chul Shin, Iksoo Choi, Sanghyuk Nam, Gyu-Seog Cho, Dongsun Sheen, Seung-Ho Pyi, Jongmoo Choi, Sung-Kye Park, Jinwoong Kim, Seokkiu Lee, S. Aritome, Sung-Joo Hong · 2012
A new Metal Control Gate Last process (MCGL process) has been successfully developed for the DC-SF (Dual Control gate with Surrounding Floating gate cell)[1] three-dimensional (3D) NAND flash memory. The MCGL process can realize a low resistive tungsten (W) metal word-line with high-k IPD, a low damage on tunnel oxide/IPD, and a preferable FG shape. And also, a conventional bulk erase can be used, replaced GIDL erase in BiCS[3][4], due to direct connection between channel poly and p-well by the channel contact holes. Therefore, by using MCGL process, high performance and high reliability of DC-SF cell can be achieved for MLC/TLC 256Gb/512Gb 3D NAND flash memories.