A 20ns CMOS functionable gate array with a configurable memory
Tadashi Sano, S. Matsukuma, Kenji Hashimoto, Yoshito Ohuchi, O. Kudo, Hiroyuki Yamamoto · 1983
A CMOS gate array with 4,368 gates and 2,304 bits of configurable memory, using 1.5μm design rules, will be discussed. The memory can change word × bit configuration as well as to increase the gate array function.