A self-learning digital neural network using wafer-scale LSI
Masahiro Yasunaga, Naohiro Masuda, Masayoshi Yagyu, Masayuki ASAI, Kouichi Shibata, Masatoshi OOYAMA, M. Yamada, T. Sakaguchi, Mana Hashimoto · IEEE Journal of Solid-State Circuits · 1993
A large-scale, dual-network architecture using wafer-scale integration (WSI) technology is proposed. By using 0.8 mu m CMOS technology, up to 144 self-learning digital neurons were integrated on each of eight 5 in silicon wafers. Neural functions and the back-propagation (BP) algorithm were mapped to digital circuits. The complete hardware system packaged more than 1000 neurons within a 30 cm cube. The dual-network architecture allowed high-speed learning at more than 2 gigaconnections updated per second (GCUPS). The high fault tolerance of the neural network and proposed defect-handling techniques overcame the yield problem of WSI. This hardware can be connected to a host workstation and used to simulating a wide range of artificial neural networks. Signature verification and stock price prediction have already been demonstrated with this hardware.>