A novel highly flexible network multi-processor optimised for reconfigurable devices
Grigoris Raptis, Ioannis Papaefstathiou, Konstantinos Georgopoulos, Charalampos Manifavas · 2013
Although chip speed has increased exponentially over the past years, increasing a processor's speed to achieve performance speedup seems to be a way of the past. The new direction for achieving faster processing is using multiple cores in one single chip, where the cores share the work load and operate in-parallel. This paper presents the development and implementation of a 16-Core Parallel Network Processor, in Reconfigurable Logic (Field-Programmable Gate Array (FPGA)); its highly flexible architecture allows it to be utilized in numerous different FPGAs from low-cost, low-power, to high-cost, high-performance and the speedup achieved grows linearly with the silicon resources available. It has been based on an efficient single-core network processor, already presented in [1]. The processor operates at 10, 100, 1000 Mbps Ethernet speeds and it can be implemented in numerous distinct state-of-the-art FPGAs.