ALU logic synthesis using templates
Shigeru Takagi · Systems and Computers in Japan · 1986
Abstract This paper presents a method of automatic synthesis for ALU circuit based on functional specification. The ALU to be synthesized is specified by a table of functions as well as control codes indicating the selection of each function, and the bitwidth of the data. If the functional specification is expanded directly into the two‐level form, the number of conjunctive terms will become prohibitively large. As a result, the method aims at a multilevel realizaization of ALU, and a model (template) representing the essence of the logic structure of ALU is constructed. The logic expressions for parts of the template are derived from the given functional specification by modification and manipulation of logic expressions. After simplifying partial logic expressions, the lejics are combined. By the proposed method, 32‐bit ALU with 32 logic functions is realized in approximately 40 s using a computer of 2 MIPS. The synthesized logic has a quality comparable to the one by manual design. There can be various ways of defining the template, and by using different templates, various kinds of ALU's can be constructed for the same functional specification.