A hierarchical approach test vector generation
S.J. Chandra, Janak H. Patel · 1987
Given a combinational network and a specific stuck-at fault to be detected, there are several approaches to generating a test vector. However, most of these approaches fail to exploit the hierarchy inherent in any complex digital design. This paper presents a hierarchical approach to test vector generation. HIPODEM: A test generation system based on this approach is presented. General procedures to perform forward implication and backtracing in a hierarchical framework are discussed in detail. Experimental results obtained from test runs on both flat-level and hierarchical circuits are compared. For the circuits tried, generating tests from a hierarchical description proved to be faster than doing it from a flat level description of the circuit.