Random pattern testable design with partial circuit duplication and IDDQ testing
Hiroshi Yokoyama, Xiaoqing Wen, Hideo Tamamoto · Systems and Computers in Japan · 1999
The Built-In Self-Test (BIST) method has been proposed as a Design for Testability (DFT) approach in order to reduce the difficulty of LSI testing. Pseudo-random testing is suitable for BIST because the test can be performed at low cost with little hardware overhead. However, a large number of test patterns is usually required to achieve sufficient fault coverage in random testing, since not all circuits are random pattern testable. In this paper, we present an innovative method for improving random pattern testability of logic circuits by partial circuit duplication and IDDQ testing. The fundamental idea is to use IDDQ testing to detect random pattern resistant faults by using the difference between the duplicated part of a circuit and the original part. Experimental results on benchmark circuits show that high fault coverage can be achieved with a very small amount of hardware overhead. © 1999 Scripta Technica, Syst Comp Jpn, 30(5): 18–27, 1999