Interfacing slave designs to FASTBUS: practical experience
Robert W. Downing, J.J. Hoeflich, V. Simaitis, L. Pregernig · IEEE Transactions on Nuclear Science · 1988
The authors have designed a number of FASTBUS slave modules, using a standard interface circuit and standard design-verification tools based on computer-aided-engineering (CAE) techniques. They describe the standard interface and the design and verification methodology. The interface logic for FASTBUS slaves is divided into three blocks: the slave control logic, slave address/data logic, and slave support logic. The control logic is a hybrid chip that handles the protocol portion of the interface. The slave address/data logic includes the functions performed by the address/data interface chip and additional data-path related components, i.e. registers, buffers, and level shifters. The support logic is additional logic necessary to glue the other blocks and application logic together.>