Symbolic analysis of faulty logic circuits in the presence of correlated gate failures
Srdjan Brkić, Predrag Ivaniš, Goran T. Djordjević, Bane V. Vasic · 2013
In this paper we present a method for symbolic analysis of unreliable logic circuits in the presence of correlated and data-dependent gate failures, described by Markov chains. Presented probabilistic algorithm is used for the analysis of majority logic and XOR logic circuits.