AN ON-CHIP BUS MODELING AND PARAMETER SIMULATION METHOD BASED ON UTILIZATION ANALYSIS
Zaifeng Shi, TAO LUO, Yuanqing Li, YAN XU, Suying Yao · Journal of Circuits Systems and Computers · 2013
In system level design or architecture design stage of SoCs, it is important to estimate the system parameters such as bus utilization and buffer capacity. A novel bus modeling method which was derived from Markov model for obtaining these parameters of an on-chip-bus system has been proposed in this paper. This modeling approach employs Markov chain to describe the state change of the system. This method was used in architecture design verification of a video format converting (VFC) chip. By comparing the simulation result and the pessimistic estimate value, the rationality and high efficiency of this method were verified, and more than 55% of FIFOs size are saved. It is suitable for analyzing various bus systems, such as user-defined buses, industrial standard buses, multi-core and multi-bus systems.