Shift-register connections for delayed versions of m -sequences
A.N. van Luyn · Electronics Letters · 1978
A fast and simple method is introduced that can be used, both manually and in computing, to determine which linear combination of shift-register outputs corresponds to a d-bit delayed version of a maximal-length linear binary sequence. The calculation time is proportional to the logarithm of d. The method is suitable for generating large phase shifts.