Area, time, power optimization for radix-2 redundant CORDIC rotation engines
Thambipillai Srikanthan, Bimal Gisuthan, K. Vijayan Asari · Proceedings of SPIE, the International Society for Optical Engineering/Proceedings of SPIE · 1999
CORDIC rotation engines have become with primary hardware- computing modules for realization of trigonometric functions in real time digital signal processing. We propose an area- time efficient architecture for redundant CORDIC with significant power savings. The precomputation of signed digits for rotation mode leads to a reduced transition density in the Z-recurrences. This leads to a reduced switching activity that results in lower power dissipation. The parallelized generation of the signed digits in the CORDIC rotation engine results in over 30 percent savings in hardware with significant speed up of operation. As no estimates are used for the precomputation of the singed digits no correcting rotations are necessary. The number of iteration that needs to be repeated is one irrespective of the accuracy of operation needed and the scaling factor is constant. The computation of the signed digits is removed from the critical path of the design and the response time of the circuit is dependent only on the full adder delay in the CMOS technology library used for implementation. The designs for 16-bit, 24-bit and 32-bit redundant CORDIC architectures incorporating the precomputation of signed digits are presented. The architecture for precomputation of the signed digits is simulated using SYNOPSIS VSS. The functionality simulated design is synthesized with SYNOPSIS design analyzer. The switching power is estimated using SYNOPSIS DesignPower. The proposed architecture is compared with relevant designs in literature.