Efficient sequential test generation based on logic simulation
Shuo Sheng, Michael S. Hsiao · IEEE Design & Test of Computers · 2002
In this article, we present an efficient logic-simulation-based test generator that executes significantly more quickly than its fault-simulation-based counterparts. This test generator's fault coverage compares favorably with that of the latest techniques for large sequential circuits. It uses a genetic algorithm to achieve both high fault coverage and short test generation times.