A 2Gb/s network processor with a 24mW IPsec offload for residential gateways
Yukikuni Nishida, Kenji Kawai, K. Koike · 2010
A 90 nm CMOS network processor comprising dual CPUs, a packet engine (PE), and an embedded LAN switch is developed on a 7.51 × 7.75 mm2die. The network processors enable a residential gateway to forward packets at 2 Gb/s with IP security and packet filtering. By offloading the packet handling to a packet engine, the power consumption of this function is limited to 24 mW.