High throughput and hardware efficient FFT architecture for LTE application
Jienan Chen, Jianhao Hu, S. X. Li · 2012
In this paper, we propose a high throughput and hardware efficient Fast Fourier Transform (FFT) architecture for Long Term Evolution (LTE) application. The proposed enhancement delay element matrix (EDEM) which contains the mixed radix unit supports 25, 16, 9, 8, 5, 4, 3 and 2-point FFTs. The reuse technology is also applied into EDEM to reduce the hardware resource. The EDEM reduces the computation cycles significantly since the high radix decomposition method is applied. Compared with the stated of art technology, the proposed scheme improves 2×~4× throughput rate with comparable hardware cost. For all of the 35 FFT lengths in LTE applications, the computation cycles of proposed method are less than the length of FFT, which can supports the continuous flow of processing data in the same clock domain with I/O data. The speed-area product factor outperforms 2~3 times than the existed FFT processor. The proposed architecture also supports the variable length FFT.