Viterbi Decoders Generation for FPGA Platforms
Luis Alberto Luna Espinosa, L. Sanchez, Juan Iván Nieto Hipólito, Mabel Vázquez-Briseño, Aldo-Eleazar Perez-Ramos, Salvador Villarreal Reyes · 2013
In this paper, we describe a relation that allows to generate Viterbi decoders for FPGA platforms. These decoders are created from the vectors that describe the adders of a convolutional encoder with code rate 1/2. This relation has been used to implement a script in Mat lab, which generates decoders in VHDL language for an FPGA platform from a basic set of entities used to create ACS cells.