A pedagogical processor model
Will D. Gillett, Eric B. Muehrcke · 1983
This paper presents a pedagogical processor model, intended for teaching fundamental concepts about von Neumann machines. A general discussion of the desirable pedagogical properties is given, and a specific one address machine is defined. The machine has a simple architecture, supports four addressing modes, and uses a small number of hierarchically organized, fixed-field instructions. Debugging capabilities are included in the definition and can be accessed by executable instruction.