Hardware Implementation of Serial High Speed point to point Communication protocol
Rameshwari Bisen, Harish Verma, Arun Kumar Parakh · 2014
This paper presents the hardware implementation of high speed communication protocol for point to point communication. Complete hardware is coded in VHDL and implemented on Xilinx Spartan-3 XC3400 FPGA. Communications between two nodes in this protocol is based on error-checked and retransmit on error scheme. Data filtration is provided to prevent receiver to receive duplicate frame. For error detection we used CRC-8, which has good performance both in case of burst or single bit error. In this protocol CPU has very low overhead during communication. Because processing element only stores the data (pay load of transmitted message) in to transmitter FIFO and further processing like addition of other necessary information and generation of CRC is done independently by hardware designed for communication. This protocol supports the transmission of serial data at variable speed. Maximum serial transmission speed is achieved 10Mbps with 40 MHz quartz clock. Time taken to transmit complete frame is 14 s.