I DDQ Detectable Bridges in Combinational CMOS Circuits
Eugeni Isern, Joan Figueras · VLSI design · 1997
Undetectable stuck‐at faults in combinational circuits are related to the existence of logic redundancy ( s-redundancy ). Similarly, logically equivalent nodes may cause some bridging faults to become undetectable by I D D Q testing. An efficient method for the identification and removal of such functionally equivalent nodes ( f-redundant nodes ) in combinational circuits is presented. OBDD graphs are used to identify the functional equivalence of candidate to f‐redundancy nodes. An f‐redundancy removal algorithm based on circuit transformations to improve bridging fault testability, is also proposed. The efficiency of the identification and removal of f‐redundancy has been evaluated on a set of benchmark circuits.