Binary division algorithm and implementation in VHDL
Filip Adamec, Tomáš Frýza · 2009
This article describes a basic algorithm for a division operation. Its performance and consideration of the implementation in VHDL are discussed. There are described three possible implementations, the maximum performance in FPGAs, e.g. propagation delays and number of necessary steps to enumerate the correct result. In the conclusion the performance and necessary number of steps are compared.