Parametric time delay modeling for floating point units
Hossam A. H. Fahmy, Albert A. Liddicoat, Michael J. Flynn · Proceedings of SPIE, the International Society for Optical Engineering/Proceedings of SPIE · 2002
A parametric time delay model to compare floating point unit implementations is proposed. This model is used to compare a previously proposed floating point adder using a redundant number representation with other high-performance implementations. The operand width, the fan-in of the logic gates and the radix of the redundant format are used as parameters to the model. The comparison is done over a range of operand widths, fan-in and radices to show the merits of each implementation.