Design and implementation of a family of reliable systolic correlators
Gavin Brebner, R. Ramaswamy, David Aspinall · IEE Proceedings E Computers and Digital Techniques · 1990
A methodology is presented for adding varying amounts of fault and defect tolerance to computing systems based on linear pipelines. This is illustrated by the example of a novel-architecture correlator/convolver. This new device is described fully, followed by a description of our fault-tolerant technique, based on the idea of an ‘interconnection harness’. It is then shown how this methodology can be applied to the architecture of our correlator giving a family of high-speed devices with varying amount of fault tolerance and hardware overhead. In conclusion, an actual implementation using the ES2 Solo 1200 system of one of the members of this family is described and performance/area results are given.