FPGA-Based Design and Implementation of Reduced AES Algorithm
Jun Yang, Jun Ding, Li Na, Guo Yixiong · 2010
This paper introduces the principle of AES algorithm and the detailed description and implementation on FPGA. This system aims at reduced hardware structure. Compared with the pipeline structure, it has less hardware resources and high cost-effective. And this system has high security and reliability. This AES system can be widely used in the terminal equipments.