Low capture power at-speed test in EDT environment
Elham Moghaddam, Janusz Rajski, Sudhakar M. Reddy, Xijiang Lin, Nilanjan Mukherjee, Mark Kassab · 2010
This paper presents a novel low capture power test scheme integrated with EDT (Embedded Deterministic Test) environment. The key contribution of this paper is to generate test vectors that in capture mode mimic functional operation from switching activity point of view. Experimental results presented for industrial circuits demonstrate the effectiveness of the proposed method.