A VLSI delay commutator for FFT implementation
Earl E. Swartzlander, W.K.W. Young, Senoj Joseph · 1984
The implementation of a 108,000 transistor delay/commutator circuit for realization of FFT processors achieving data rates of up to 40MHz, will be described. The circuit contains 12,288 shift register stages and about 2000 logic gates, and implemented with 2.5μm CMOS standard cell technology.