Power minimisation of VLSI wave digital filtersthrough systolic blocksize selection
Pasin Israsena, S. Summerfield · Electronics Letters · 1999
An investigation into systolic architectures for wave digital filters for low-power applications is presented. Based on a three-port adaptor implementation of the second-order section, minimum power is found using pipelining with a 2 bit block size for which the power consumption is reduced by 50% and the power-area-delay performance increased by 5 times relative to the starting, non-pipelined, implementation.