The Design and Implementation of a Hierarchical Networkon-Chip
Chorfi Chandarli Braham, Ji Weixinga, Lingyu Zhang · Procedia Engineering · 2012
Network-on-Chip (NoC) architectures represent the most viable solution for on-chip communication issues of future chip multi-processor systems. To meet performance, power and reliability requirements, which characterize future ambient intelligent applications, several NoC architectures were proposed recently. TriBA is an object-oriented chip multi-processor that supports truly parallel execution of objects from hardware. In this paper we design and implement a new router architecture for TriBA network-on-chip. The hardware architecture of the router is detailed and a new routing algorithm is described. We present the packet latency results under different traffic pattern of a 27 core TriBA-NoC model. The results show that TriBA-NoC benefits greatly from traffic locality.