Advanced circuit techniques for high-performance microprocessor and low-power DSPs
Mathew Mathew, Krishnamurthy, Anders, Hsu -, Borkar · 2004
This article presents the challenges and solutions for a high-performance microprocessors and low-power digital signal processing chips. It discusses the high-performance power-efficient execution core such as the 6.5 GHz single-rail domino 32-bit Han-Car ALU; the 4 GHz semi-dynamic 32-bit sparse-tree AGU. It also deals with leakage-tolerant register files; conditional/burn-in keeper; pseudo-static bitlines; low-power datapaths for DSP applications; and the 1 GHz 16-bit static multiplier.