NoC-aware cache design for multithreaded execution on tiled chip multiprocessors
Ahmed K. Abousamra, Alex K. Jones, Rami Melhem · 2011
In chip multiprocessors (CMPs), data access latency depends on the memory hierarchy organization, the on-chip interconnect (NoC), and the running workload. Reducing data access latency is vital to achieving performance improvements and scalability of threaded applications. Multithreaded applications generally exhibit sharing of data among the program threads, which generates coherence and data traffic on the NoC.