Signature Analysis for Test Responses of Sequential Circuits
Albrecht P. Stroele · VLSI design · 1998
Many test schemes use signature analyzers to compact the responses of a circuit under test. Unfortunately, there can be some faulty circuits with erroneous test responses but exactly the same signature as in the fault‐free case. Hence, methods are required to determine how many faults become undetectable due to aliasing. Whereas previous work concentrated on combinational circuits, this paper investigates signature analysis for a wide range of sequential circuits, where the errors in successive responses are correlated. It is shown that for almost all faults of these circuits the probability of aliasing in a signature analyzer with k bits asymptotically approaches 2−k or is 0 if a signature analyzer with an irreducible characteristic polynomial is used and certain test lengths are avoided. The limiting value can be used as a good approximation for practical test lengths. These results are particularly useful for advanced built‐in self‐test techniques with low hardware overhead.