Design methodology for self-timed VLSI systems
Paul Lister, A.M. Alhelwani · IEE Proceedings E Computers and Digital Techniques · 1985
A design methodology for self-timed VLSI systems is proposed. This includes a language for describing algorithmic behaviour which is based on the data-flow concept. A subclass of Petri nets is introduced to model the designed system, and a refinement technique is presented that allows for the synthesis of correct-by-construction systems. Finally, a systematic means for implementing the design is given.