A high performance 64Gb MLC NAND flash memory in 20nm CMOS technology
Jin‐Su Park, Byoung-Sung You, Sang-Don Lee, Kwang-Ho Baek, Chun-Woo Jeon, Tai-Kyu Kang, Jaeho Lee, Minsu Kim, Dae-il Choi, Jaewon Choi, Hyun Jeong, Jong-woo Kim, Eun-seong Jang, Taeyun Kim, Chang-Hyuk Lee, Jong-Gi Nam, Bong-Seok Han, Kun-Ok Ahn, Ki-hyun Bae · 2012
A 64Gb MLC NAND flash memory on 20nm CMOS technology has been developed. 135mm2chip size is realized by 1-sided All-Bit-Line architecture and 128 cells in a string. 25MB/s program throughput with 2-bit/cell is achieved by reducing BL resistance and pump output loading using new BL control method and multi-split block decoder. This device also supports 400MB/s high speed interface.