An output compression scheme for handling X-states from over-clocked delay tests
Adit D. Singh, Chao Han, Xi Qian · 2010
Faster-than-rated clock delay tests aimed at targeting small delay defects can generate a large number of unknown X values because the test response for all paths longer than the (over clocked) test clock period must be marked X. Current test compression techniques cannot efficiently handle such a large number of X responses. We propose a simple multiplexing scheme for output test data compression which avoids any compaction of the test response. Just as input test compression techniques take advantage of the fact that there are only a small number of ¿care¿ bits in the ATPG generated test inputs, our new approach leverages the fact that not all the output bits in the captured test response need be observed. In most cases, observing only selected 2-5% of the test response bits captured in the scan chains can still result in the same target test coverage as when all output bits are observed, albeit at the expense of requiring some additional TDF delay test vectors. Since no test result compaction is performed, the new approach is capable of handling an unbounded number of X-states during aggressive delay testing. Experimental results show that test time/data volume reduction of 10X or better appears viable.