A new bit-serial systolic multiplier over GF(2/sup m/)
Bing Bing Zhou · IEEE Transactions on Computers · 1988
A bit-serial systolic array has been developed to computer multiplications over GF(2/sup m/). In contrast to a previously designed systolic multiplier, this algorithm allows the input elements to center a linear systolic array in the same order, and the system only requires one control signal.>