Optimizing DSP circuits by a new family of arithmetic operators
Javier Hormigo, Julio Villalba · 2014 48th Asilomar Conference on Signals, Systems and Computers · 2014
This paper presents a new family of arithmetic operators to optimize the implementation of circuits for digital signal processing. They are based on using a new fixed-point format which allows performing rounding to nearest as the same cost as truncation. Thanks to the use of rounding, the word-length optimization may improve significantly respect to using conventional units and truncation. That reduction means a simultaneous improvement of area, delay, and, consequently, power consumption. As an example, several FIR filters have been tested, and an area reduction up to 50% along with a speed improvement up to 42% has been obtained.