A new hardware architecture for sampling the exponential distribution
Tarek Ould Bachir, Mohamad Sawan, Jean‐Jules Brault · Conference proceedings - Canadian Conference on Electrical and Computer Engineering · 2008
Hardware acceleration in high performance computing context is of growing interest, particularly in the field of Monte Carlo methods where the resort to FPGA technology enhances execution speed by several orders. For this purpose, a particular attention has been given lately to hardware-based non-uniform random variate generators. In this paper we present both a hardware-dedicated decision tree technique for the generation of exponential variates and a derived architecture implemented in FPGA. The proposed design passes the χ2test with a p-value of 0.5499 and ensures absence of serial correlation. The exponential random number generator reaches 375 MHz on a Xilinx Virtex II Pro FPGA and occupies about 3 % of the available space.