A low-price platform to test digital integrated circuits using FPGA
Leonardo Londero de Oliveira, J.P. dos S Martins, André L. Aita · 2005
In this paper, we describe a low-price method to test integrated circuits using the same test vectors in the gate, transistor and device levels of abstraction. A test program often generates hundreds of thousands of different test vectors applied at a frequency of several megahertz over several hundred milliseconds. Production testers are large machines that take up their own room and are very expensive (typically well over $1 million). Either the customer, or the ASIC manufacturer, or booth, develop the test program. Two things are necessary before virtual integration and test can be accomplished. The first is the ability to simulate the hardware at speeds sufficient to make software execution a reality. In most cases, this means that the hardware simulation performance must be increased by a factor of at least 1000 over current execution speeds. The second is the need to bring the debug and development environments of the hardware and software closer together. In order to describe here the proposed method, the test of a circuit is presented. The DUT (device under test) used as example is a digital integrated circuit that implements a novel architecture for multiplication. The multiplier integrated circuit was designed using Xilinx and Mentor Graphics tools and fabricated in AMI/spl I.bar/C5F technology. Results have shown that the idea can be easily extended to 16 or 32 bits and the frequency operation is directly dependent of the FPGA board used. Test vectors up to 50 MHz were being employed with a depth equal to 100.