Cache-aware task scheduling on multi-core architecture
Teng-Feng Yang, Chung-Hsiang Lin, Chia-Lin Yang · 2010
Cache utilization is critical to performance in a chip-multiprocessor(CMP) system. A typical cache hierarchy in a CMP contains per-core private cache and a large shared last-level cache. How to schedule tasks to improve cache utilization is challenging. In this paper, we propose a cache-aware scheduling policy which improves cache performance by considering data reuse, memory footprint of co-scheduled tasks, and coherency misses. The proposed scheduling policy is implemented in the scheduler of Threading Building Blocks(TBB), which is a multithreading library from Intel. The experimental results show that the proposed cache-aware task scheduling policy achieves up to 45% execution time reduction compared with the original TBB scheduler.