Synthesis of a unified unit for evaluating an application-specific set of elementary functions
Liangwei Ge, Zhenan Tang, Kaiyu Wang, Ming Cao, Wencong Zou, Dong Liu · 2010
Fast and accurate evaluation of elementary functions (e.g. 1/ x , log,3√x, and 1/√x) is vital in many computation intensive applications. This paper presents a synthesis system of a unified hardware unit for evaluating a custom subset of elementary functions. Based on some latest algorithms of software library and new design principles that exploit the parallelism of reconfigurable hardware, fast and compact datapath is automatically generated. The proposed system also enables rapid design space exploration by allowing designers to modify the constraints on each function (e.g. precision, delay, area, etc.). For an arbitrary set of logarithm functions and power series, accuracy around 0.6 ulp (unit of last place) is achieved at double precision, which is 0.3 ulp more accurate than Pentium®, and the speed is 30% faster than Itanium®. The result is simulated by 80nm process.