Mixed Memory Type Realizations of Sequential Machines
Peter D. Weiner, T. A. Dolotta · IEEE Transactions on Computers · 1969
In this note, we examine the problem of finding good state assignments when mixed memory type realizations (i.e., including mixtures of delay and trigger flip-flop memories) are permitted. Specifically, we describe situations that take advantage of this extra degree of design freedom, and we indicate how to modify two existing algorithms to determine such mixed realizations systematically.